Encoding:

Format:

SHRAV[_R].PH 

SHRAV.PH   rd, rt, rs

SHRAV_R.PH rd, rt, rs

Purpose:

Shift Right Arithmetic Variable Vector Pair Halfwords

Element-wise arithmetic right shift of two independent halfwords in a vector data type by a variable number of bits, with optional rounding.

Description:

rd = sign_extend(rnd16(rt31..16 >> rs3..0) || rnd16(rt15..0 >> rs3..0))

The two right-most halfword values in register rt are each independently shifted right, with each value's original sign bit duplicated into the most-significant bits emptied by the shift. In the non-rounding variant of this instruction, the two independent results are then written to the corresponding halfword elements of destination register rd.

In the rounding variant of this instruction, a 1 is added at the most-significant discarded bit position before the results are written to destination register rd.

The shift amount sa is given by the four least-significant bits of register rs; the remaining bits of rs are ignored.

For both instructions, the sign of the left-most halfword result is sign-extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

SHRAV.PH:
   tempB15..0 = shift16RightArithmetic( GPR[rt]31..16, GPR[rs]3..0 )
   tempA15..0 = shift16RightArithmetic( GPR[rt]15..0, GPR[rs]3..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
SHRAV_R.PH:
   tempB15..0 = rnd16ShiftRightArithmetic( GPR[rt]31..16, GPR[rs]3..0 )
   tempA15..0 = rnd16ShiftRightArithmetic( GPR[rt]15..0, GPR[rs]3..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled